Standardcell Layout Engineer

Perform standard cell Layout Design and library development across advanced semiconductor process technologies.

Design and optimize custom standard cells using FINFET technology process rules.

Utilize industry-standard EDA tools including Cadence, Innovus, and Calibre for layout drafting and verification.

Run physical verification routines, ensuring standard cell layouts pass strict DRC, LVS, and reliability requirements.

Collaborate with library characterization and physical design teams to optimize cell density, delay, and power consumption.

Maintain organized standard cell GDSII libraries, layout verification logs, and design rule check reports.

Bachelor's or Master's degree in Electronics Engineering, Microelectronics, or VLSI.

3–5 Yrs of hands-on experience in Standard cell layout design and physical verification.

Good knowledge of Standard cell layout design and practical FINFET technology experience.

Technical proficiency in tools like Calibre, Cadence, and Innovus.