Senior Staff Engineer

Lead physical design execution from RTL/netlist synthesis through place and route (P&R) to final GDSII generation.

Drive static timing analysis (STA), setup/hold timing closure, signal integrity (SI) analysis, and multi-corner multi-mode (MCMM) signoff.

Develop and maintain automated design flows and productivity scripts using Shell, Perl, TCL, and Makefile environments.

Execute floorplanning, power grid design, clock tree synthesis (CTS), routing, and design rule checking (DRC/LVS).

Collaborate with DFT, CAD, packaging, and library teams to optimize silicon power, performance, and area (PPA).

Prepare sign-off checklists, timing reports, physical verification summaries, and post-layout debug logs.

Bachelor’s / Master’s Degree in Electronics Engineering, VLSI Design, Microelectronics, or Electrical Engineering.

3-5 Yrs of hands-on physical design and timing closure experience in advanced semiconductor technology nodes.

Strong proficiency in scripting languages (TCL, Perl, Shell) and Make flows.

Deep knowledge of synthesis, P&R tools, STA signoff, and physical verification (DRC/LVS/ERC).