Principal Layout Engineer

Take chip top ownership of analog, mixed-signal, and Digital integrated circuit (IC) layouts as a layout technical expert.

Manage complex custom layouts across advanced technology Nodes, including High Voltage (HV) and Power Management circuits.

Perform physical verification checks including LVS (Layout Versus Schematic) and DRC (Design Rule Checking) using Cadence EDA tools.

Optimize floorplanning, routing, substrate noise isolation, and electromigration mitigation across top-level chip architectures.

Collaborate with circuit design leads to ensure layout performance meets power, performance, and area (PPA) specifications.

Maintain complete layout design documentation, verification sign-off logs, and physical design rule guidelines.

Bachelor's or Master's degree in Electrical, Electronics & Communication Engineering, or VLSI Design.

1-3 Yrs of extensive experience in IC layout design, physical verification, and chip-top ownership.

Deep technical expertise in Cadence tools, advanced technology nodes, high voltage/power management layouts, and LVS/DRC checks.

Strong leadership capability, physical verification discipline, and technical mentoring skills.