Design Verification Engineer

Contribute to developing Cisco's progressive data center networking silicon and ASIC solutions.

Build scalable, reusable testbenches using SystemVerilog and Universal Verification Methodology (UVM).

Execute functional verification across complex high-speed networking protocols including Ethernet, PCIE, TCP, and Wireless IPs.

Write and maintain verification scripts utilizing Perl and Python to automate test suites and coverage reports.

Collaborate closely with ASIC design and architecture teams to debug RTL failures and achieve 100% functional and code coverage closure.

Maintain complete verification plans, test suite documentation, regression logs, and bug tracking reports.

Bachelor's or Master's degree in Electronics & Communication Engineering, Electrical Engineering, VLSI Design, or related fields.

1-3 Yrs of core experience in ASIC design verification, testbench development, and UVM methodology.

Deep technical expertise in SystemVerilog, UVM, high-speed protocols (Ethernet, PCIE), and scripting (Perl).

Excellent analytical problem-solving habits, RTL debugging skills, and technical domain leadership.